Technical Field
The present disclosure relates to an LDMOS semiconductor device and to a method for manufacture thereof.
Description of the Related Art
As is known, some applications of MOSFET power devices (or power MOSFETs) operate said MOSFET power devices at high switching frequencies. An example is that of electrical switches used in the field of high-frequency pulse-width modulation (PWM). In order to maximize the efficiency of the device, it is expedient for the levels of dynamic performance to exhibit a negligible loss of power during the switching operations. Said condition is obtained by minimizing the values of capacitance of the parasitic capacitors internal to said devices. Particular attention is directed at minimization of the gate-to-drain capacitance CGD, since said capacitance CGD determines the duration of the period of transient of the voltage signal during switching. It is hence of importance to minimize the value of capacitance CGD so as to minimize the power losses of the MOSFET power device. A parameter, which is strictly linked to the parasitic capacitance and is typically used for characterizing the efficiency of a MOSFET power device during switching, is the gate charge QG. In fact, the value of gate charge QG furnishes an estimate of the amount of current to supply to the gate terminal of the MOSFET power device to obtain switching of said device from the off state (in which it does not conduct electric current) to the on state (in which there is conduction of electric current between the source and drain terminals).
Lateral double-diffused MOSFETs (LDMOSs) can advantageously be used in a wide range of frequencies, with powers that range from a few watts to a few hundred watts. A classic LDMOS structure comprises a substrate, which has, in lateral sectional view, a horizontal sequence constituted by a low-resistance laterally diffused area (of a P+ type, referred to as “sinker”), a source region, a gate region, and a light-doped-drain (LDD) region that provides the drain terminal. The LDD region moreover faces a surface of the substrate. Said structure of a known type forms, for obvious reasons, an elementary cell with a large pitch.
Lateral MOSs have been amply studied, and known in the literature are techniques of minimization of the internal capacitances and information on how to obtain values of drain-to-source on-state resistance (RDS_ON) that are comparable with the values of the technology of trench field-effect transistors (also known as “trench-FETs”).
FIG. 1 shows an LDMOS transistor of a known type, in particular described in U.S. Pat. No. 7,936,007. With reference to FIG. 1, represented therein is a lateral sectional view of a structure designed to minimize the pitch of the base cell of an LDMOS. In this case, an LDMOS transistor 1 includes a substrate 2, having a top surface 2a and a bottom surface 2b opposite to one another, in which an LDD region 3 extends from the top surface 2a of the substrate 2 to the bottom surface 2b (without actually reaching the bottom surface 2b). In an area corresponding to the bottom surface 2b a drain region 4 is present. The LDD region 3 is obtained by forming, starting from the top surface 2a of the substrate 2, implanted regions 5a and 5b, of an N type, self-aligned to the gate terminal 6 and interposed between two gate terminals 6 set alongside one another. A sinker region 7 extends in the substrate 2, in areas corresponding to body regions 10, underneath source regions 9. A conductive layer 8 extends above, and electrically insulated from, the gate terminal 6, and penetrates into the substrate 2 until it contacts the source region 9 and the sinker region 7.
In order to minimize the parasitic capacitance between the gate terminal 6 and the LDD region 3, the structure shown in FIG. 1 may be modified in such a way that the conductive layer 8 extends over the side wall 6a of the gate terminal 6, above the LDD region 3. By connecting the conductive layer 8 to a ground reference terminal, a conductive “shield” is formed, designed to attenuate the phenomenon known as “hot-carrier injection” (HCI) and improve gate/drain decoupling. In addition, it is expedient to envisage a dielectric layer 11 in order to separate the portion of the conductive layer 8 that extends above the LDD region 3 from the top surface 2a of the substrate 2. Said dielectric layer 11 of separation preferably has a thickness in the region of 100-200 nm. A solution in this direction is the one described in U.S. Pat. No. 7,589,378 (not shown in the figure). In this case, an LDMOS transistor with LDD surface region is proposed in which a conductive shield extends over the gate terminal and alongside it, above the LDD region, and separated from the latter by means of a dielectric layer. In this way, a reduction of the electrical field is obtained with consequent benefit in terms of increase of the on-state drain-to-source resistance RDS_ON and attenuation of the value of gate-to-drain capacitance. As mentioned previously, the solution with LDD surface region imposes constraints on the minimum pitch that can be obtained, which can be reduced further only at the expense of the value of breakdown voltage, which drops considerably.
As an alternative, more complex processes may be used, of the type described in U.S. Pat. No. 7,829,947, wherein a power LDMOS has a field-oxide region underneath the gate region in order to minimize the capacitance between the gate region and the LDD region. Said device, however, presents major manufacturing difficulties in order to control overlapping between the LDD region and the gate region.